This application claims the priority benefit of Taiwan application serial no. 90109367, filed on Apr. 19, 2001.
1. Field of Invention
This invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a mask read-only memory (Mask ROM).
2. Description of Related Art
Because the non-volatile characteristic of the mask read-only memory is able to retain the memory when the power source is interrupted, many electrical products, therefore, are equipped with this type of memory to maintain a normal operation between the xe2x80x9conxe2x80x9d and the xe2x80x9coffxe2x80x9d of these electrical products. The mask read-only memory is one the most fundamental types of the read-only memory. In order to facilitate the fabrication process, the transistor is normally not being removed. Instead, a mask layer is used to determine whether the transistor and the metal line are connected or through an ion implantation process to adjust the threshold voltage to achieve the purpose of controlling the xe2x80x9conxe2x80x9d and the xe2x80x9coffxe2x80x9d of the memory. This type of ion implantation is also known as the code implantation process.
According to the aforementioned fabrication method for a mask read-only memory, a significant modification to the fabrication method is unnecessary even changes are made to the products. This type of fabrication method is thus appropriate for mass production since only the masks are to be modified. As a matter of fact, an intermediate product can be manufactured first. The intermediate product is then programmed upon the receipt of a purchase order to efficiently reduce the delivery time. The new applications for some devices employ other types of memory or logic device in combination with the mask read-only memory, for example an embedded static random access memory (embedded SRAM) in combination with the mask read-only memory to increase the performance of the chip.
FIG. 1 is a schematic, cross-sectional view, showing the manufacturing of a mask read-only memory according to the prior art.
As shown in FIG. 1, an ion implantation is conducted to implant an N-type dopants on a P-type silicon substrate 100 to form a plurality of equally spaced bit lines 102, wherein the space between the bit lines forms the channel region. Thereafter, thermal oxidation is conducted, under various oxidation rates, to form a thicker oxide layer 104a on the bit lines 102 and a thinner oxide layer 104b on the channel region. The thermal oxidation is conducted, for example, approximately at 850 degree Celsius for 30 minutes. A polysilicon layer is further deposited and etched to a defined pattern to form the word lines 106. Subsequently, a programming process is conducted to form a mask layer 108 on the word line 106, exposing the channel region 110 to be coded. An implantation of the P-type or the N-type dopant is conducted, according to the characteristic of the transistor, to complete the code implantation.
According to the conventional approach in forming the mask read-only memory, the thermal oxidation process has to be long enough to grow the oxide layer 104a with a sufficient thickness. Therefore, the distance between the bit lines 102 can not be small in order to prevent the diffusion of dopant of the bit lines 102 during the long thermal oxidation process and to prevent the short channel effect. As a result, the conventional fabrication method can not effectively reduce the distance between the bit lines 102 and increase integration.
The present invention provides a fabrication method for a mask read-only memory, wherein a gate oxide layer is formed on the provided substrate. A mask layer is then formed on the gate oxide layer, followed by performing an ion implantation to form a plurality of equally spaced bit lines. Thereafter, a thermal process is conducted to convert the oxide layer to a denser oxide layer. A plurality of word lines, which is perpendicular to the bit lines, is then formed on the denser oxide layer. A mask layer is further formed on the plurality of word lines, exposing the channel to be coded. An ion implantation is then conducted to the channel to complete the fabrication of a mask read-only memory.
The present invention provides the formation of an oxide layer on a substrate before the formation of bit lines. An oxide layer with a sufficient thickness is thus formed without a long thermal process. The diffusion of dopant due to the long thermal process, leading to a great bit line junction area is prevented. The problem of not being able to reduce the distance between the bit lines and to increase integration is thereby avoided.
The present invention provides the formation of a gate oxide layer on the substrate, followed by performing a thermal process to form a denser oxide layer. The required processing time is thus greatly reduced to lower the thermal budget.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.